1. Field
Example embodiments relate to an interposer chip and a multi-chip package having the interposer chip. More particularly, example embodiments relate to an interposer chip that may be used for electrically connecting two semiconductor chips, which may have different sizes, with each other. Example embodiments also relate to a multi-chip package having the interposer chip.
2. Description of the Related Art
Various semiconductor fabrication processes may be performed on a semiconductor substrate to form a plurality of semiconductor chips. Packaging processes may be performed on the semiconductor chips to form semiconductor packages. In order to increase a storage capacity of the semiconductor packages, multi-chip packages may be formed to include a plurality of stacked semiconductor chips. The stacked semiconductor chips may be electrically connected to each other via conductive wires. However, if the semiconductor chips have different sizes, directly connecting the stacked semiconductor chips with each other using the conductive wires may be difficult due to a length limit of the conductive wire.
Interposer chips may be used to electrically connect semiconductor chips having different sizes. A conventional interposer chip may include an insulating substrate and conductive patterns formed on the insulating substrate. The conductive patterns and the semiconductor chips may be electrically connected with each other via the conductive wires. However, because conventional interposer chips may not have a common pad, an electrical connection between conductive wires and a conductive pattern may not be accurately identified. That is, whether a test current may flow or not to the conductive pattern through the conductive wire may not be identified when the conductive wire is connected to the conductive pattern.